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LSR (SPC700): Difference between revisions
From SnesLab
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|[[Negative Flag|N]] | |[[Negative Flag|N]] | ||
Revision as of 05:02, 27 November 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Accumulator | 5C | 1 byte | 2 cycles | ||||
| Direct Page | 4B | 2 bytes | 4 cycles | ||||
| Direct Page Indexed by X | 5B | 2 bytes | 5 cycles | ||||
| Absolute | 4C | 3 bytes | 5 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | |||
LSR (Logical Shift Right) is an SPC700 instruction that shifts its operand one bit to the right, dividing it by two. The least significant bit is shifted into the carry flag. A zero is shifted into the most significant bit.
The official manual has the bit shift operators for LSR pointing the wrong way.
See Also
External Links
- Official Super Nintendo development manual on LSR: Appendix C-7 of Book I