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Interrupt Disable Flag: Difference between revisions
From SnesLab
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(COP also sets it) |
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The '''Interrupt Disable Flag''' (I) exists on the [[65c816]] as bit 2 of the [[status register]]. | The '''Interrupt Disable Flag''' (I) exists on the [[65c816]] as bit 2 of the [[status register]]. | ||
[[SEI]] sets it and [[CLI]] clears it. ([[SEP]] and [[REP]] can as well.) | [[SEI]] sets it and [[CLI]] clears it. ([[SEP]] and [[REP]] can as well.) [[COP]] sets it too. | ||
This flag is automatically set whenever the processor begins servicing an interrupt. | This flag is automatically set whenever the processor begins servicing an interrupt. | ||
Revision as of 19:39, 9 August 2024
The Interrupt Disable Flag (I) exists on the 65c816 as bit 2 of the status register.
SEI sets it and CLI clears it. (SEP and REP can as well.) COP sets it too.
This flag is automatically set whenever the processor begins servicing an interrupt.
BRK ignores it.
There are no BIS or BIC instructions that examine this flag (though there is an unrelated BIC (Super FX) instruction).
See Also
Reference
- Pickens, John. NMOS 6502 Opcodes. http://www.6502.org/tutorials/6502opcodes.html#IFLAG