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CLD: Difference between revisions

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(flowed REP into body)
(flowed BRK into body)
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CLD
CLD
</pre>
</pre>
[[BRK]] handlers do not need CLD because BRK also clears the decimal flag.


To clear more than one flag at the same time, use [[REP]].
To clear more than one flag at the same time, use [[REP]].
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* [[CLC]]
* [[CLC]]
* [[CLV]]
* [[CLV]]
* [[BRK]]


=== External Links ===
=== External Links ===

Revision as of 01:57, 10 August 2024

Basic Info
Addressing Mode Opcode Length Speed
Implied (type 2) D8 1 byte 2 cycles
Flags Affected
N V M X D I Z C
. . . . 0 . . .

CLD is a 65x instruction that clears the decimal mode flag, switching the processor back into binary mode so ADC and SBC will operate normally.

No other flags are affected.

Syntax

CLD

BRK handlers do not need CLD because BRK also clears the decimal flag.

To clear more than one flag at the same time, use REP.

See Also

External Links