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Official Documentation Quick Links: Difference between revisions
From SnesLab
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* [https://archive.org/details/SNESDevManual/book2/page/n81 Variable-Length Bit Processing] | * [https://archive.org/details/SNESDevManual/book2/page/n81 Variable-Length Bit Processing] | ||
* [https://archive.org/details/SNESDevManual/book2/page/n85 DMA] | * [https://archive.org/details/SNESDevManual/book2/page/n85 DMA] | ||
==== Section 2 - Super FX ==== | ==== Section 2 - Super FX ==== | ||
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* [https://archive.org/details/SNESDevManual/book2/page/n103 Memory Mapping] | * [https://archive.org/details/SNESDevManual/book2/page/n103 Memory Mapping] | ||
* [https://archive.org/details/SNESDevManual/book2/page/n107 GSU Internal Register Configuration] | * [https://archive.org/details/SNESDevManual/book2/page/n107 GSU Internal Register Configuration] | ||
* [https://archive.org/details/SNESDevManual/book2/page/n117 GSU Program Execution] | |||
* [https://archive.org/details/SNESDevManual/book2/page/n123 Instruction Execution] | |||
* [https://archive.org/details/SNESDevManual/book2/page/n135 Data Access] | |||
* [https://archive.org/details/SNESDevManual/book2/page/n139 GSU Special Functions] | |||
* [https://archive.org/details/SNESDevManual/book2/page/n157 Chapter 9 Description of Instructions] | * [https://archive.org/details/SNESDevManual/book2/page/n157 Chapter 9 Description of Instructions] | ||
**[https://archive.org/details/SNESDevManual/book2/page/n159 ADC] | **[https://archive.org/details/SNESDevManual/book2/page/n159 ADC] | ||
Revision as of 17:24, 16 May 2023
Book I
Section 1 - Approval Process
- Chapter 1. NOA Licensed Software Approval Process
- Chapter 2. Super NES Software Submission Requirements
Section 2 - Super NES Software
- Chapter 1. Introduction
- Chapter 2. Object (OBJ)
- Chapter 3. Background (BG)
- Chapter 4. Mosaic
- Chapter 5. Rotation/Enlargement/Reduction
- Chapter 6. Window (Window Mask)
- Chapter 7. Main/Sub Screen
- Chapter 8. CG Direct Select
- Chapter 9. H-Pseudo 512
- Chapter 10. Complementary Multiplication (Signed Multiplication)
- Chapter 11. H/V Counter Latch
- Chapter 12. Offset Change
- Chapter 13. Standard Controller
- Chapter 14. Programmable I/O Port
- Chapter 15. Absolute Multiplication/Division
- Chapter 16. H/V Count Timer
- Chapter 17. Direct Memory Access (DMA)
- Chapter 18. Interlace
- Chapter 19. H-512 Mode (BG Mode 5 & 6)
- Chapter 20. OBJ 33's Lines Over & Priority Order
- Chapter 21. CPU Clock and Memory Mapping
- Chapter 22. Super NES Functional Operation
- Chapter 23. System Flowchart
- Chapter 24. Programming Cautions
- Chapter 25. Documented Problems
- Chapter 26. Register Clear (Initial Settings)
- Chapter 27. PPU Registers
- INIDISP
- OBJSEL
- OAMADDL / OAMADDH
- OAM DATA
- BG MODE aka BGMODE
- MOSAIC
- BG1SC / BG2SC / BG3SC / BG4SC
- BG1NBA / BG34NBA
- BG1H0FS / BG1V0FS
- BG2H0FS / BG2V0FS / BG3H0FS / BG3V0FS / BG40FS / BG4V0FS
- VMAINC
- VMADDL / VMADDH
- VMDATAL / VMDATAH
- M7SEL
- M7A / M7B / M7C / M7D / M7X / M7Y
- CGADD / CGDATA
- W12SEL / W34SEL / WOBJSEL
- WH0 / WH1 / WH2 / WH3
- WBGLOG / WOBJLOG
- TM
- TS
- TMW
- TSW
- CGSWEL
- CGADSUB
- COLDATA
- SETINI
- MPYL / MPYM / MPYH
- SLHV
- OAMDATA
- VMDATAL / VMDATAH
- CGDATA
- OPHCT / OPVCT
- STA77 / STA78
- APUIO0 / APUIO1 / APUIO2 / APUIO3
- VMDATA
- VMADDL / VMADDM / VMADDH
Section 3 - Super NES Sound
- Chapter 1. SNES Sound Source Outline
- Chapter 2. BRR (Bit Rate Reduction)
- Chapter 3. I/O Ports
- Chapter 4. Control Register
- Chapter 5. Timers
- Chapter 6. DSP Interface Register
- Chapter 7. Register Used
- Chapter 8. CPU Organization
- Chapter 9. Sound Programming Cautions
Tables of Appendix
- Appendix A. PPU Registers
- Appendix B. CPU Registers
- Appendix C SPC700 Commands
- Appendix D. Data Transfer Procedure
Book II
Section 1 - Super Accelerator (SA-1)
- Super Accelerator System Functions
- Configuration of SA-1
- Super Accelerator Memory Map
- SA-1 Internal Register Configuration
- Chapter. Multi-Processor Processing
- Chapter 6. Character Conversion
- Arithmetic Function
- Variable-Length Bit Processing
- DMA
Section 2 - Super FX
- Chapter 1 Introduction to Super FX
- GSU Functional Operation
- Memory Mapping
- GSU Internal Register Configuration
- GSU Program Execution
- Instruction Execution
- Data Access
- GSU Special Functions
- Chapter 9 Description of Instructions
- ADC
- ADD
- ALT1
- ALT2
- ALT3
- AND
- ASR
- BCC
- BCS
- BEQ
- BGE
- BIC
- BLT
- BMI
- BNE
- BPL
- BRA
- BVC
- BVS
- CACHE
- CMODE
- CMP
- COLOR
- DEC
- DIV2
- FMULT
- FROM
- GETB
- GETBH
- GETBL
- GETBS
- GETC
- HIB
- IBT
- INC
- IWT
- JMP
- LDB
- LDW
- LEA
- LINK
- LJMP
- LM
- LMS
- LMULT
- LOB
- LOOP
- LSR
- MERGE
- MOVE
- MOVEB
- MOVES
- MOVEW
- MULT
- NOP
- NOT
- OR
- PLOT
- RAMB
- ROL
- ROMB
- ROR
- RPIX
- SBC
- SBK
- SEX
- SM
- SMS
- STB
- STOP
- STW
- SUB
- SWAP
- TO
- UMULT
Section 3 - DSP/DSP-1
- Chapter 1 Introduction to DSP1
- Chapter 2 Command Summary
- Chapter 3 Parameter Data Type
- Chapter 4 Use of DSP1
- Description of DSP1 Commands
- Chapter 6 Math Functions and Equations
Section 4 - Accessories
- The Super NES Super Scope System
- Principles of the Super NES Super Scope
- Super NES Super Scope Functional Operation
- Chapter 4. Super NES Super Scope Receiver Functions
- Chapter 5. Graphics
- Chapter 6. Super NES Mouse Specifications
- Chapter 7. Using the Standard BIOS
- Chapter 8 Programming Cautions
- MultiPlayer 5 Specifications
- MultiPlayer 5 Supplied BIOS
- Super NES Parts List
- Index for Book I
- Index for Book II