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Book I

Table of Contents - page i
List of Figures - page v
List of Tables - page ix
Preface - page 1
Confidentiality Agreement - page 2

Section 1 - Approval Process

Chapter 1. NOA Licensed Software Approval Process - page 1-1-1

Authorized Software Developer Requirements - page 1-1-2

Chapter 2. Super NES Software Submission Requirements - page 1-2-1

Software Verification - page 1-2-3
Software Submission Check List - page 1-2-6
This Page Intentionally Left Blank - page 1-2-7
Super NES Software Specification - page 1-2-9
Instructions for Super NES Software Specification - page 1-2-10
Character Code List for Game Title Registration - page 1-2-13
ROM Registration Data Specification - page 1-2-14
Description of ROM Registration Data Specification - page 1-2-15
Data Storage on Floppy Disk - page 1-2-22
Super NES Cartridge PCB List - page 1-2-23
SHVC Cartridge List (21 Map, Production Type) - page 1-2-38
This Page Intentionally Left Blank - page 1-2-39
Price Quote Request for Super NES Cartridge - page 1-2-40

Section 2 - Super NES Software

Chapter 1. Introduction - page 2-1-1
- Super NES Display - page 2-1-2
Chapter 2. Object (OBJ) - page 2-2-1
- Setting Example - page 2-2-2
Chapter 3. Background (BG) - page 2-3-1
- Setting Example - page 2-3-2
Chapter 4. Mosaic - page 2-4-1
Chapter 5. Rotation/Enlargement/Reduction - page 2-5-1
- Setting Example - page 2-5-2
Chapter 6. Window (Window Mask) - page 2-6-1
Chapter 7. Main/Sub Screen - page 2-7-1
- Screen Addition/Subtraction - page 2-7-2
- Setting Example - page 2-7-3
- Color Constant Addition/Subtraction - page 2-7-4
- Color Window - page 2-7-5
Chapter 8. CG Direct Select - page 2-8-1
Chapter 9. H-Pseudo 512 - page 2-9-1
Chapter 10. Complementary Multiplication (Signed Multiplication) - page 2-10-1
Chapter 11. H/V Counter Latch - page 2-11-1
Chapter 12. Offset Change - page 2-12-1
Chapter 13. Standard Controller - page 2-13-1
- Setting Example - page 2-13-2
Chapter 14. Programmable I/O Port - page 2-14-1
Chapter 15. Absolute Multiplication/Division - page 2-15-1
Chapter 16. H/V Count Timer - page 2-16-1
Chapter 17. Direct Memory Access (DMA) - page 2-17-1
- Setting Example - page 2-17-3
Chapter 18. Interlace - page 2-18-1
Chapter 19. H-512 Mode (BG Mode 5 & 6) - page 2-19-1
Chapter 20. OBJ 33's Lines Over & Priority Order - page 2-20-1
- Priority Order Shifting - page 2-20-2
Chapter 21. CPU Clock and Memory Mapping - page 2-21-1
- Super NES CPU Memory Map - page 2-21-2
- Super NES Memory Map (Mode 20) - page 2-21-3
- Super NES Memory Map (Mode 21) - page 2-21-4
- Super NES Memory Map (Mode 25, ROM Size Greater than 32 Mbits only) - page 2-21-5
Chapter 22. Super NES Functional Operation - page 2-22-1
- Super NES Functional Block Diagram - page 2-22-2
Chapter 23. System Flowchart - page 2-23-1
Chapter 24. Programming Cautions - page 2-24-1
- Edge Detection - page 2-24-5
- Sample Program - page 2-24-6
- Alternate Method - page 2-24-7
- This Page Intentionally Left Blank - page 2-24-8
Chapter 25. Documented Problems - page 2-25-1
- Problem 2 - page 2-25-2
Chapter 26. Register Clear (Initial Settings) - page 2-26-1
Chapter 27. PPU Registers - page 2-27-1
- INIDISP - Initial Settings for Screen - page 2-27-1
- OBJSEL - Object Size & Object Data Area Designation - page 2-27-1
- OAMADDL / OAMADDH - Address for Accessing OAM - page 2-27-2
- OAM DATA - Data for OAM write - page 2-27-2
- BG MODE aka BGMODE - Background Mode & Character Size Settings - page 2-27-3
- MOSAIC - Size & Screen Designation for Mosaic Display - page 2-27-3
- BG1SC / BG2SC / BG3SC / BG4SC - Address for Storing SC-Data of each BG & SC Size Designation - page 2-27-4
- BG1NBA / BG34NBA - BG Character Area Designation - page 2-27-5
- BG1H0FS / BG1V0FS - H/V Scroll Value Designation for BG-1 - page 2-27-5
- BG2H0FS / BG2V0FS / BG3H0FS / BG3V0FS / BG40FS / BG4V0FS - H/V Scroll Value Designation for BG-2,3,4 page 2-27-6
- VMAINC - VRAM Address Increment Value Designation - page 2-27-6
- VMADDL / VMADDH - Address for VRAM Read & Write - page 2-27-7
- VMDATAL / VMDATAH - Data for VRAM Write - page 2-27-7
- M7SEL - Initial Setting in Screen Mode-7 - page 2-27-8
- M7A / M7B / M7C / M7D / M7X / M7Y - page 2-27-9
- CGADD / CGDATA - Address for CG-RAM Read and Write - page 2-27-11
- W12SEL / W34SEL / WOBJSEL - Window Mask Settings - page 2-27-12
- WH0 / WH1 / WH2 / WH3 - Window Position Designation - page 2-27-12
- WBGLOG / WOBJLOG - Mask Logic Settings for Window-1 & 2 on Each Screen - page 2-27-13
- TM - Main Screen Designation - page 2-27-14
- TS - Sub Screen Designation - page 2-27-14
- TMW - Window Mask Designation for Main Screen - page 2-27-15
- TSW - Window Mask Designation for Sub Screen - page 2-27-15
- CGSWEL - Initial Settings for Fixed Color Addition or Screen Addition - page 2-27-16
- CGADSUB - page 2-27-17
- COLDATA - Fixed Color Data for Fixed Color Addition/Subtraction - page 2-27-18
- SETINI - Screen Initial Setting - page 2-27-19
- MPYL / MPYM / MPYH - Multiplication Result - page 2-27-20
- SLHV - Software Latch for H/V Counter - page 2-27-20
- OAMDATA - Read Data from OAM - page 2-27-21
- VMDATAL / VMDATAH - Read Data from VRAM - page 2-27-21
- CGDATA - Read Data from CG-RAM - page 2-27-22
- OPHCT / OPVCT - H/V Counter Data by External or Software Latch - page 2-27-22
- STAT77 / STAT78 - PPU Status Flag & Version Number - page 2-27-23
- APUIO0 / APUIO1 / APUIO2 / APUIO3 - Communication Port with APU - page 2-27-24
- WMDATA - Data to consecutively read from and write to WRAM - page 2-27-25
- WMADDL / WMADDM / WMADDH - Address to consecutively read and write WRAM - page 2-27-25

Chapter 28. CPU Registers - page 2-28-1
- NMITIMEN Enable Flag for V-Blank, Timer Interrupt & Standard Controller Read - page 2-28-1
- WRIO - Programmable I/O Port - page 2-28-1
- WRMPYA / WRMPYB - Multiplier & Multiplicand by Multiplication - page 2-28-2
- WRDIVL / WRDIVH / WRDIVB - Divisor & Dividend by Divide - page 2-28-2
- HTIMEL / HTIMEH - H-Count Timer Settings - page 2-28-3
- VTIMEL / VTIMEH - V-Count Timer Settings - page 2-28-3
- MDMAEN - Channel Designation for General Purpose DMA & Trigger (Start) - page 2-28-4
- HDMAEN - Channel Designation for H-DMA - page 2-28-5
- MEMSEL - Access Cycle Designation in Memory - page 2-28-5
- RDNMI - NMI Flag By V-Blank & Version Number - page 2-28-6
- TIMEUP - IRQ Flag by H/V Count Timer - page 2-28-6
- HVBJOY - H/V Blank Flag & Standard Controller Enable Flag - page 2-28-7
- RDIO - Programmable I/O Port - page 2-28-7
- RDDIVL / RDDIVH - Quotient of Divide Result - page 2-28-8
- RDMPYL / RDMPYH - Product of Multiplication Result or Remainder of Divide Result - page 2-28-8
- STD CNTRRL1L / 1H / 2L/2H/3L/3H/4L/4H - Data for Standard Controller - page 2-28-9