Official Documentation Quick Links

• Chapter 1. NOA Licensed Software Approval Process
• Chapter 2. Super NES Software Submission Requirements

• Chapter 1. Introduction
• Chapter 2. Object (OBJ)
• Chapter 3. Background (BG)
• Chapter 4. Mosaic
• Chapter 5. Rotation/Enlargement/Reduction
• Chapter 6. Window (Window Mask)
• Chapter 7. Main/Sub Screen
• Chapter 8. CG Direct Select
• Chapter 9. H-Pseudo 512
• Chapter 10. Complementary Multiplication (Signed Multiplication)
• Chapter 11. H/V Counter Latch
• Chapter 12. Offset Change
• Chapter 13. Standard Controller
• Chapter 14. Programmable I/O Port
• Chapter 15. Absolute Multiplication/Division
• Chapter 16. H/V Count Timer
• Chapter 17. Direct Memory Access (DMA)
• Chapter 18. Interlace
• Chapter 19. H-512 Mode (BG Mode 5 & 6)
• Chapter 20. OBJ 33's Lines Over & Priority Order
• Chapter 21. CPU Clock and Memory Mapping
• Chapter 22. Super NES Functional Operation
• Chapter 23. System Flowchart
• Chapter 24. Programming Cautions
• Chapter 25. Documented Problems
• Chapter 26. Register Clear (Initial Settings)
• Chapter 27. PPU Registers
• Chapter 28. CPU Registers

• Chapter 1. SNES Sound Source Outline
• Chapter 2. BRR (Bit Rate Reduction)
• Chapter 3. I/O Ports
• Chapter 4. Control Register
• Chapter 5. Timers
• Chapter 6. DSP Interface Register
• Chapter 7. Register Used
• Chapter 8. CPU Organization
• Chapter 9. Sound Programming Cautions

• Appendix A. PPU Registers
• Appendix B. CPU Registers
• Appendix C SPC700 Commands
• Appendix D. Data Transfer Procedure