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TCLR1 (SPC700): Difference between revisions
From SnesLab
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!colspan="8"|Basic Info | !colspan="8"|Basic Info | ||
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|'''Speed''' | |'''Speed''' | ||
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| | |[[Absolute Addressing | Absolute]] | ||
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|3 byte | |3 byte | ||
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!colspan="8"|Flags | !colspan="8"|Flags Affected | ||
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|N | |[[Negative Flag|N]] | ||
|V | |[[Overflow Flag|V]] | ||
|P | |[[Direct Page Flag|P]] | ||
|B | |[[Break Flag|B]] | ||
|H | |[[Half-Carry Flag|H]] | ||
|I | |[[Interrupt Enable Flag|I]] | ||
|Z | |[[Zero Flag|Z]] | ||
|C | |[[Carry Flag|C]] | ||
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'''TCLR1''' is an [[SPC700]] instruction that tests and clears memory bits using the [[accumulator]]. For every set bit in the accumulator, the corresponding memory bit is cleared. | |||
=== See Also === | === See Also === | ||
* [[TSET1]] | * [[TSET1]] | ||
* [[CLR1]] | |||
* [[TRB]] | |||
=== External Links === | === External Links === | ||
# Official Nintendo documentation on TCLR1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | |||
# subparagraph 8.2.3.2 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:SPC700]] | [[Category:SPC700]] | ||
[[Category:Bit Operation Commands]] | [[Category:Bit Operation Commands]] | ||
[[Category:Three-byte Instructions]] | |||
Latest revision as of 13:21, 29 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute | 4E | 3 byte | 6 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | ||
TCLR1 is an SPC700 instruction that tests and clears memory bits using the accumulator. For every set bit in the accumulator, the corresponding memory bit is cleared.
See Also
External Links
- Official Nintendo documentation on TCLR1: Table C-18 in Appendix C-9 of Book I
- subparagraph 8.2.3.2 of page 3-8-8, lbid.