Overflow Flag

The Overflow Flag (V) is bit 6 of the status register. It is affected only by the following eight instructions:

ADC (indicates signed sum overflowed)
SBC (indicates signed difference underflowed)
CLV (always clears it)
BIT (becomes bit 6 or bit 14 of operand except in immediate addressing)
PLP
RTI
SEP (might set it)
REP (might clear it)

Here is how it behaves:

When the accumulator is 8 bits wide, V indicates whether the sum/difference of ADC/SBC is outside the range of -128 to 127.
When the accumulator is 16 bits wide, V indicates whether the result of ADC/SBC is outside the range of -32768 to 32767.

Adding a positive and negative integer together never sets the overflow flag because the sum has a smaller magnitude than either addend.

It may be the most misunderstood flag of the 65c816 and the 6502.^[2][3]

There is no SEV instruction to directly set the overflow flag, but the 6502 and 65c02 do have a hardware signal to set it. Unfortunately this hardware signal was removed on the 65c816 (or fortunately, as now it can no longer get set by accident.)

On the SPC700 it can be cleared with CLRV and is set whenever the half-carry flag is set.

BVC and BVS both examine the overflow flag to decide whether or not to branch.

The overflow flag is invalid in decimal mode on the NMOS 6502, but it is valid in the 65c816's decimal mode.

References

Eyes & Lichty, page 439
lbid, "Branching Based on the Overflow Flag" on page 150
Clark, Bruce. http://www.6502.org/tutorials/vflag.html
Shirriff, Ken. The 6502 overflow flag explained mathematically. https://www.righto.com/2012/12/the-6502-overflow-flag-explained.html?m=1
lbid. https://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html?m=1
Labiak, William. Page 108.
Pickens, John. NMOS 6502 Opcodes. http://www.6502.org/tutorials/6502opcodes.html#VFLAG
https://forums.nesdev.org/viewtopic.php?t=6331
Table 7-1 Caveats of 65c816 datasheet

See Also

References