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Master Clock: Difference between revisions
From SnesLab
(→See Also: machine cycle) |
(→See Also: pixel clock) |
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* [[APU oscillator]] | * [[APU oscillator]] | ||
* [[CIC Clock]] | * [[CIC Clock]] | ||
* [[Pixel Clock]] | |||
* [[FastROM]] | * [[FastROM]] | ||
* [[SlowROM]] | * [[SlowROM]] | ||
Revision as of 18:05, 18 August 2024
The Master Clock is 21.48 MHz on NTSC and 21.28 MHz on PAL.
The master clock (X1) is in region A4 of the jwdonal schematic