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STY: Difference between revisions

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|'''Speed'''
|'''Speed'''
|+
|+
|absolute
|[[Absolute]]
|8C
|8C
|3 bytes
|3 bytes
|4 cycles*
|4 cycles*
|+
|+
|direct page
|[[Direct Page Addressing|Direct Page]]
|84
|84
|2 bytes
|2 bytes
|3 cycles*
|3 cycles*
|+
|+
|direct page indexed Y
|[[Direct Page Indexed by X]]
|96
|94
|2 bytes
|2 bytes
|4 cycles*
|4 cycles*
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!colspan="9"|Flags Affected
!colspan="9"|Flags Affected
|+
|+
|N
|[[Negative Flag|N]]
|V
|[[Overflow Flag|V]]
|M
|[[M Flag|M]]
|X
|[[X Flag|X]]
|D
|[[Decimal Flag|D]]
|I
|[[I Flag|I]]
|Z
|[[Zero Flag|Z]]
|C
|[[Carry Flag|C]]
|+
|+
|.
|.
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'''STY''' (Store Y) is a 65x instruction that stores the value of the [[Y index register]].  STY takes one additional cycle when the index registers are 16 bits wide, in all [[addressing modes]]. In both [[direct page addressing]] modes only, STY takes another additional cycle if the low byte of the [[direct page register]] is nonzero.  
'''STY''' (Store Y) is a 65x instruction that stores the value of the [[Y index register]].  If Y is 16-bit, its high byte is stored to the effective address plus one.
 
No flags are affected.
 
==== Syntax ====
<pre>
STY addr
STY dp
STY dp, X
</pre>
 
==== Cycle Penalties ====
* STY takes one additional cycle when the index registers are 16 bits wide, in all [[addressing modes]].
* In both [[direct page addressing]] modes only, STY takes another additional cycle if the low byte of the [[direct page register]] is nonzero.  


=== See Also ===
=== See Also ===
* [[LDY]]
* [[STA]]
* [[STA]]
* [[STX]]
* [[STX]]
* [[STZ]]
* [[STZ]]
* [[TYA]]
* [[TYX]]


=== External Links ===
=== External Links ===
* [[Eyes & Lichty]] page on STY: https://archive.org/details/0893037893ProgrammingThe65816/page/n532
* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/506 page 506] on STY
* [[Labiak]] page on STY: https://archive.org/details/Programming_the_65816/page/n197
* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n197 page 187] on STY
* [[MCS6500 Manual]] page on STY: https://archive.org/details/mos_microcomputers_programming_manual/page/n115
* 7.3 on [[MCS6500 Manual]], [https://archive.org/details/mos_microcomputers_programming_manual/page/n115 page 97] on STY
* [[Carr]] page on STY: https://archive.org/details/6502UsersManual/page/n287
* [[Carr]], [https://archive.org/details/6502UsersManual/page/n287 page 274] on STY
* [[Leventhal]] page on STY: https://archive.org/details/6502-assembly-language-programming/page/n147
* [[Leventhal]], [https://archive.org/details/6502-assembly-language-programming/page/n147 page 3-98] on STY
* snes9x implementation of STY: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1302
* snes9x implementation of STY: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1302
* undisbeliever on STY: https://undisbeliever.net/snesdev/65816-opcodes.html#sty-store-index-register-y-to-memory
* undisbeliever on STY: https://undisbeliever.net/snesdev/65816-opcodes.html#sty-store-index-register-y-to-memory
* Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#STY


[[Category:ASM]]
[[Category:ASM]]
[[Category:Group Three Instructions]]
[[Category:Group Three Instructions]]
[[Category:Inherited from 6502]]
[[Category:Inherited from 6502]]
[[Category:Load/Store Instructions]]

Latest revision as of 06:41, 22 August 2024

Basic Info
Addressing Mode Opcode Length Speed
Absolute 8C 3 bytes 4 cycles*
Direct Page 84 2 bytes 3 cycles*
Direct Page Indexed by X 94 2 bytes 4 cycles*
Flags Affected
N V M X D I Z C
. . . . . . . .

STY (Store Y) is a 65x instruction that stores the value of the Y index register. If Y is 16-bit, its high byte is stored to the effective address plus one.

No flags are affected.

Syntax

STY addr
STY dp
STY dp, X

Cycle Penalties

See Also

External Links