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'''TCLR1''' is an [[SPC700]] instruction that tests and clears bits.
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!colspan="8"|Basic Info
!colspan="8"|Basic Info
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|'''Speed'''
|'''Speed'''
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|[[Absolute Addressing | Absolute]]
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!colspan="8"|Flags Clobbered
!colspan="8"|Flags Affected
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|[[Negative Flag|N]]
|[[Overflow Flag|V]]
|[[Direct Page Flag|P]]
|[[Break Flag|B]]
|[[Half-Carry Flag|H]]
|[[Interrupt Enable Flag|I]]
|[[Zero Flag|Z]]
|[[Carry Flag|C]]
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'''TCLR1''' is an [[SPC700]] instruction that tests and clears memory bits using the [[accumulator]].  For every set bit in the accumulator, TCLR1 clears the corresponding memory bit.
==== Syntax ====
<pre>
TCLR1 !abs
</pre>
Where abs is any address in the whole 64K [[bank]] of [[ARAM]].


=== See Also ===
=== See Also ===
* [[TSET1]]
* [[TSET1]]
* [[CLR1]]
* [[TRB]]
=== External Links ===
# Official Nintendo documentation on TCLR1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I]
# subparagraph 8.2.3.2 of [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid.
# anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L606


[[Category:ASM]]
[[Category:ASM]]
[[Category:SPC700]]
[[Category:SPC700]]
[[Category:Bit Operation Commands]]
[[Category:Three-byte Instructions]]

Latest revision as of 17:40, 11 August 2024

Basic Info
Addressing Mode Opcode Length Speed
Absolute 4E 3 bytes 6 cycles
Flags Affected
N V P B H I Z C
N . . . . . Z .

TCLR1 is an SPC700 instruction that tests and clears memory bits using the accumulator. For every set bit in the accumulator, TCLR1 clears the corresponding memory bit.

Syntax

TCLR1 !abs

Where abs is any address in the whole 64K bank of ARAM.

See Also

External Links

  1. Official Nintendo documentation on TCLR1: Table C-18 in Appendix C-9 of Book I
  2. subparagraph 8.2.3.2 of page 3-8-8, lbid.
  3. anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L606