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Inter-PPU Bus: Difference between revisions
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[[File:inter-ppu bus.png|thumb|The Inter-PPU bus, straddling regions A2 to B3 in the [[jwdonal schematic]]]] | |||
The '''Inter-PPU Bus''' connects [[S-PPU1]] and [[S-PPU2]] together. It is not connected to anything else. The trace names are: | The '''Inter-PPU Bus''' connects [[S-PPU1]] and [[S-PPU2]] together. It is not connected to anything else. The trace names are: | ||
* CHR3 | * CHR3 | ||
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* /5MIN - 5 MHz In | * /5MIN - 5 MHz In | ||
* /5MOUT - 5 MHz Out | * /5MOUT - 5 MHz Out | ||
=== See Also === | |||
* [[PPU Bus]] | |||
[[Category:Buses]] | [[Category:Buses]] | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
Latest revision as of 22:41, 1 August 2023
The Inter-PPU bus, straddling regions A2 to B3 in the jwdonal schematic
The Inter-PPU Bus connects S-PPU1 and S-PPU2 together. It is not connected to anything else. The trace names are:
- CHR3
- CHR2
- CHR1
- CHR0
- PRIO1
- PRIO0
- COLOR2
- COLOR1
- COLOR0
- /VCLD
- /HCLD
- FIELD
- /OVER
- /5MIN - 5 MHz In
- /5MOUT - 5 MHz Out