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TCLR1 (SPC700): Difference between revisions
From SnesLab
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=== External Links === | === External Links === | ||
# Official Nintendo documentation on TCLR1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | # Official Nintendo documentation on TCLR1: Table C-18 in [https://archive.org/details/SNESDevManual/book1/page/n234 Appendix C-9 of Book I] | ||
# https://archive.org/details/SNESDevManual/book1/page/n186 | # [https://archive.org/details/SNESDevManual/book1/page/n186 page 3-8-8], lbid. | ||
Revision as of 06:16, 18 December 2023
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute | 4E | 3 byte | 6 cycles | ||||
| Flags Affected | |||||||
|---|---|---|---|---|---|---|---|
| N | V | P | B | H | I | Z | C |
| . | . | . | . | . | . | ||
TCLR1 is an SPC700 instruction that tests and clears memory bits using the accumulator. For every set bit in the accumulator, the corresponding memory bit is cleared.
See Also
External Links
- Official Nintendo documentation on TCLR1: Table C-18 in Appendix C-9 of Book I
- page 3-8-8, lbid.