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STY: Difference between revisions
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==== Cycle Penalties ==== | |||
* STY takes one additional cycle when the index registers are 16 bits wide, in all [[addressing modes]]. | * STY takes one additional cycle when the index registers are 16 bits wide, in all [[addressing modes]]. | ||
* In both [[direct page addressing]] modes only, STY takes another additional cycle if the low byte of the [[direct page register]] is nonzero. | * In both [[direct page addressing]] modes only, STY takes another additional cycle if the low byte of the [[direct page register]] is nonzero. | ||
Latest revision as of 06:41, 22 August 2024
| Basic Info | |||||||
|---|---|---|---|---|---|---|---|
| Addressing Mode | Opcode | Length | Speed | ||||
| Absolute | 8C | 3 bytes | 4 cycles* | ||||
| Direct Page | 84 | 2 bytes | 3 cycles* | ||||
| Direct Page Indexed by X | 94 | 2 bytes | 4 cycles* | ||||
| Flags Affected | ||||||||
|---|---|---|---|---|---|---|---|---|
| N | V | M | X | D | I | Z | C | |
| . | . | . | . | . | . | . | . | |
STY (Store Y) is a 65x instruction that stores the value of the Y index register. If Y is 16-bit, its high byte is stored to the effective address plus one.
No flags are affected.
Syntax
STY addr STY dp STY dp, X
Cycle Penalties
- STY takes one additional cycle when the index registers are 16 bits wide, in all addressing modes.
- In both direct page addressing modes only, STY takes another additional cycle if the low byte of the direct page register is nonzero.
See Also
External Links
- Eyes & Lichty, page 506 on STY
- Labiak, page 187 on STY
- 7.3 on MCS6500 Manual, page 97 on STY
- Carr, page 274 on STY
- Leventhal, page 3-98 on STY
- snes9x implementation of STY: https://github.com/snes9xgit/snes9x/blob/master/cpuops.cpp#L1302
- undisbeliever on STY: https://undisbeliever.net/snesdev/65816-opcodes.html#sty-store-index-register-y-to-memory
- Pickens, John. http://www.6502.org/tutorials/6502opcodes.html#STY