Accumulator Addressing: Difference between revisions

Revision as of 13:10, 24 July 2024

There are six instructions that support Accumulator Addressing on the 65c816. They are:

ASL (opcode 0A)
DEC (opcode 3A)
INC (opcode 1A)
LSR (opcode 4A)
ROL (opcode 2A)
ROR (opcode 6A)

They all are one byte long. None of them write to external memory. They are all read-modify-write instructions.

In this admode, the accumulator is the operand.^[3] In native mode when the m flag is clear, the accumulator is 16 bits wide. Otherwise it is 8 bit (when m is set or in emulation mode).

Syntax

ROR
RORA
ROR A

Interestingly, XBA is not considered to use accumulator addressing. Less surprisingly, neither are the transfer instructions which include the accumulator as an operand. But XCN on the SPC700 is considered to use accumulator addressing.

References

Eyes & Lichty, page 387: https://archive.org/details/0893037893ProgrammingThe65816/page/387
page 126, lbid: https://archive.org/details/0893037893ProgrammingThe65816/page/126
section 3.5.8 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf
Clark, Bruce. http://www.6502.org/tutorials/65c816opcodes.html#5.6

@@ Line 19: / Line 19: @@
 </pre>
-Interestingly, [[XBA]] is not considered to use accumulator addressing.  But [[XCN]] on the [[SPC700]] is.
+Interestingly, [[XBA]] is not considered to use accumulator addressing.  Less surprisingly, neither are the transfer instructions which include the accumulator as an operand.  But [[XCN]] on the [[SPC700]] is considered to use accumulator addressing.
 === See Also ===