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Memory/Accumulator Select: Difference between revisions

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(ADC, SBC)
(ORA, AND, EOR)
Line 11: Line 11:
* [[RTI]]
* [[RTI]]


It affects the behavior of (incomplete list):
It affects the behavior of (possibly incomplete list):


* [[LDA]]
* [[LDA]]
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* [[ROR]]
* [[ROR]]
* [[ROL]]
* [[ROL]]
* [[ORA]]
* [[AND]]
* [[EOR]]


But it does not affect [[XBA]], [[TDC]], or [[TCD]].
But it does not affect [[XBA]], [[TDC]], or [[TCD]].

Revision as of 23:14, 9 August 2024

The Memory/Accumulator Select (M) flag exists in the processor status register (bit 5) of the 65c816. It indicates whether the accumulator is 8 or 16 bits wide:

  • When clear, the accumulator is 16 bits wide. It can only be clear in native mode.
  • When set, the accumulator is 8 bits wide, but the high byte (B) is still retained. This is the case after reset because the processor is in emulation mode.

It can be affected by:

It affects the behavior of (possibly incomplete list):

But it does not affect XBA, TDC, or TCD.

There are no BMS or BMC instructions that examine this flag.

See Also

Reference