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TRB: Difference between revisions

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===== Cycle Penalties =====
==== Cycle Penalties ====
* In both [[addressing modes]], TRB takes two extra cycles if the accumulator is 16 bits wide.
* In both [[addressing modes]], TRB takes two extra cycles if the accumulator is 16 bits wide.
* In [[direct page addressing]], TRB takes another extra cycle if the low byte of the [[direct page register]] is nonzero.
* In [[direct page addressing]], TRB takes another extra cycle if the low byte of the [[direct page register]] is nonzero.

Latest revision as of 17:50, 23 August 2024

Basic Info
Addressing Mode Opcode Length Speed
Absolute 1C 3 bytes 6 cycles*
Direct Page 14 2 bytes 5 cycles*
Flags Affected
N V M X D I Z C
. . . . . . Z .

TRB (Test and Reset Bits) is a 65c816 instruction that tests and resets bits using the accumulator. For each set bit in the accumulator, TRB clears the corresponding memory bit.

TRB performs a logical AND (conjunction) and the zero flag is set or cleared to reflect whether the conjunction is zero. The conjunction itself is discarded.

Syntax

TRB addr
TRB dp

Cycle Penalties

See Also

External Links