Overflow Flag

The Overflow Flag (V) is affected only by the following eight instructions:

ADC (indicates signed sum overflowed)
SBC (indicates signed difference underflowed)
CLV (always clears it)
BIT
PLP
RTI
SEP (might set it)
REP (might clear it)

Here is how it behaves:

When the accumulator is 8 bits wide, V indicates whether the sum/difference of ADC/SBC is outside the range of -128 to 127.
When the accumulator is 16 bits wide, V indicates whether the result of ADC/SBC is outside the range of -32768 to 32767.

It may be the most misunderstood flag of the 65c816 and the 6502.^[2] It is bit 6 of the status register.

There is no SEV instruction to directly set the overflow flag, but the 6502 and 65c02 do have a hardware signal to set it. Unfortunately this hardware signal was removed on the 65c816.

On the SPC700 it can be cleared with CLRV and is set whenever the half-carry flag is set.

References

Eyes & Lichty, page 439: https://archive.org/details/0893037893ProgrammingThe65816/page/439
Clark, Bruce. http://www.6502.org/tutorials/vflag.html
Shirriff, Ken. https://www.righto.com/2012/12/the-6502-overflow-flag-explained.html?m=1
lbid. https://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html?m=1
Labiak. https://archive.org/details/Programming_the_65816/page/n118
Pickens, John. NMOS 6502 Opcodes. http://www.6502.org/tutorials/6502opcodes.html#VFLAG

See Also

References