TCLR1 (SPC700)

Basic Info
Addressing Mode	Opcode	Length	Speed
Absolute	4E	3 bytes	6 cycles

Flags Affected
N	V	P	B	H	I	Z	C
N	.	.	.	.	.	Z	.

TCLR1 is an SPC700 instruction that tests and clears memory bits using the accumulator. For every set bit in the accumulator, the corresponding memory bit is cleared.

Syntax

TCLR1 !abs

Where abs is any address in the whole 64K bank of ARAM.

See Also

• TSET1
• CLR1
• TRB

External Links

1. Official Nintendo documentation on TCLR1: Table C-18 in Appendix C-9 of Book I
2. subparagraph 8.2.3.2 of page 3-8-8, lbid.
3. anomie: https://github.com/yupferris/TasmShiz/blob/master/spc700.txt#L606