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CPU Data Bus: Difference between revisions
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The '''CPU Data Bus''', (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a [[DMA]]. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram" on page 2-22-2 of the official documentation. [1] | The '''CPU Data Bus''', (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a [[DMA]]. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram" on page 2-22-2 of the official documentation. [1] It is connected to: | ||
* [[S-CPU]] | |||
* [[WRAM]] | |||
* [[SPC700]] | |||
* [[Cartridge Slot]] | |||
* [[PPU1]] | |||
* [[PPU2]] | |||
* [[Expansion Port]] | |||
=== External Links === | === External Links === | ||
Revision as of 21:13, 22 May 2023
The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram" on page 2-22-2 of the official documentation. [1] It is connected to: