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X Index Register: Difference between revisions
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The '''X Index Register''' exists on 65x processors and often holds the current index when iterating over things. | The '''X Index Register''' exists on 65x processors and often holds the current index when iterating over things. It can be incremented or decremented by one with [[INX]] or [[DEX]], but there is no instruction to add or subtract more than one. | ||
On the [[S-SMP]] it is always 8 bits wide. It is the divisor for division commands.<sup>[2]</sup> | On the [[S-SMP]] it is always 8 bits wide. It is the divisor for division commands.<sup>[2]</sup> | ||
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=== See Also === | === See Also === | ||
* [[LDX]] | * [[LDX]] | ||
* [[STX]] | * [[STX]] | ||
Revision as of 02:18, 1 August 2024
The X Index Register exists on 65x processors and often holds the current index when iterating over things. It can be incremented or decremented by one with INX or DEX, but there is no instruction to add or subtract more than one.
On the S-SMP it is always 8 bits wide. It is the divisor for division commands.[2]
On the 65c816, it may be 8 or 16 bits wide. Indexing may cross bank boundaries.[1]
Unlike the Y index register, the value of the stack pointer can be transferred to/from X. See TXS and TSX.
See Also
References
- https://wilsonminesco.com/816myths
- 8.1.2 of page 3-8-4 of Book I of the official Super Nintendo development manual