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CPU Data Bus: Difference between revisions
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The '''CPU Data Bus''', (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a [[DMA]]. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram" | The '''CPU Data Bus''', (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a [[DMA]]. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to: | ||
* [[S-CPU]] | * [[S-CPU]] | ||
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=== External Links === | === External Links === | ||
* [1] https://archive.org/details/SNESDevManual/book1/page/n98 | * [1] [https://archive.org/details/SNESDevManual/book1/page/n98 page 2-22-2] of the official Super Nintendo development manual | ||
[[Category:Traces]] | [[Category:Traces]] | ||
[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Buses]] | [[Category:Buses]] | ||
Revision as of 15:51, 8 July 2023
The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:
External Links
- [1] page 2-22-2 of the official Super Nintendo development manual