We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
VRAM: Difference between revisions
From SnesLab
(preferring north as in northbridge) |
(5A22 must access VRAM through I/O) |
||
| Line 6: | Line 6: | ||
The two chips can be referred to as "A" and "B", after the lines of the [[VRAM Data Bus]] VDA0~7 and VDB0~7. | The two chips can be referred to as "A" and "B", after the lines of the [[VRAM Data Bus]] VDA0~7 and VDB0~7. | ||
VRAM is not connected to [[Address Bus A]], so the [[5A22]] must access it through I/O ports. | |||
=== See Also === | === See Also === | ||
Revision as of 02:17, 17 December 2023
VRAM chip B in region B2 of the jwdonal schematic (directly north of chip A)
There are two VRAM chips on the SNES motherboard, both connected to S-PPU1. They are both SRAM and each 32K x 8 bit (32,768 bytes) in size, for a total of 65,536 bytes (one bank).
One chip holds the low bytes of the 16-bit words, the other chip holds the high bytes.
The two chips can be referred to as "A" and "B", after the lines of the VRAM Data Bus VDA0~7 and VDB0~7.
VRAM is not connected to Address Bus A, so the 5A22 must access it through I/O ports.
See Also
Reference
- Appendix A-1 of the official Super Nintendo development manual