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Reset Traces: Difference between revisions
From SnesLab
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* [[S-DSP]] pin 47 | * [[S-DSP]] pin 47 | ||
The trace (not pin) labeled /'''RESET''' on the [[jwdonal schematic]] is produced by pin 10 (P10) of the [[CIC]] and is what actually resets PPU2 (going into pin 34). | The trace (not pin) labeled /'''RESET''' on the [[jwdonal schematic]] is produced by pin 10 (P10) of the [[Checking Integrated Circuit|CIC]] and is what actually resets PPU2 (going into pin 34). | ||
=== See Also === | === See Also === | ||
Latest revision as of 03:39, 19 August 2024
The SNES has a few traces used in system resetting:
/RESOUT0 allows S-PPU2 to reset S-PPU1. It is produced by pin 33 of PPU2 and goes into pin 98 (/RESET) of PPU1. It is not connected to anything else.
/RESOUT1 is produced by pin 28 of S-PPU2 and passes through R74 before combining with the voltage supervisor reset output. Then, /RESOUT1 goes into these pins, all of which are labled /RESET:
- S-CPU pin 50
- WRAM pin 8
- Cartridge Slot pin 26
- S-SMP pin 37
- Expansion Port pin 19
- S-DSP pin 47
The trace (not pin) labeled /RESET on the jwdonal schematic is produced by pin 10 (P10) of the CIC and is what actually resets PPU2 (going into pin 34).