We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS

Address Bus B: Difference between revisions

From SnesLab
Jump to: navigation, search
(→‎Reference: paragraph 3.2)
(→‎Reference: hid archive URL)
Line 19: Line 19:
# https://forums.nesdev.org/viewtopic.php?p=116505#p116505
# https://forums.nesdev.org/viewtopic.php?p=116505#p116505
# Figure 2-22-1, "Super NES Functional Block Diagram" on [https://archive.org/details/SNESDevManual/book1/page/n98 page 2-22-2 of Book I]
# Figure 2-22-1, "Super NES Functional Block Diagram" on [https://archive.org/details/SNESDevManual/book1/page/n98 page 2-22-2 of Book I]
# paragraph 3.2 on https://archive.org/details/SNESDevManual/book1/page/n160
# paragraph 3.2 on [https://archive.org/details/SNESDevManual/book1/page/n160 page 3-3-2 of Book I], lbid.


[[Category:SNES Hardware]]
[[Category:SNES Hardware]]
[[Category:Traces]]
[[Category:Traces]]
[[Category:Buses]]
[[Category:Buses]]

Revision as of 18:15, 29 December 2023

Address Bus B, also known as the SNES bus, is 8-bits wide on the SNES Motherboard. Its individual address lines are labeled PA0-PA7, which stands for "peripheral address," as in S-CPU peripherals (not SNES peripherals). It is connected to:

which is the exact same set of components that the CPU Data Bus is connected to. The SNES bus is drawn in purple in the colorized jwdonal schematic. Some people like to think of Address Bus B as being 16-bits wide, with the high byte being fixed to $21.[1]

SNES Bus.png

See Also

Reference

  1. https://forums.nesdev.org/viewtopic.php?p=116505#p116505
  2. Figure 2-22-1, "Super NES Functional Block Diagram" on page 2-22-2 of Book I
  3. paragraph 3.2 on page 3-3-2 of Book I, lbid.