We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
Index Register Select: Difference between revisions
From SnesLab
(it is bit 4) |
(clarify SEP/REP/PLP) |
||
| (13 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
'''Index Register Select''' (X) is a flag in the [[processor status register]] (bit 4) of the [[65c816]]. It indicates how wide the [[index register]]s are: | '''Index Register Select''' (X) is a flag in the [[processor status register]] (bit 4) of the [[65c816]]. It indicates how wide the [[index register]]s are: | ||
* When clear, both index registers are 16 bits wide. | * When clear, both index registers are 16 bits wide. It can only be clear in [[native mode]]. | ||
* When set, both index registers are 8 bits wide. | * When set or in [[emulation mode]], both index registers are 8 bits wide. | ||
It is not possible to control the width of the two index registers individually. | It is not possible to control the width of the two index registers individually. | ||
| Line 8: | Line 8: | ||
It can be affected by: | It can be affected by: | ||
* [[REP]] | * [[REP]] (clears it if bit 4 of operand is set) | ||
* [[SEP]] | * [[SEP]] (sets it if bit 4 of operand is set) | ||
* [[PLP]] | * [[PLP]] (pops it off the [[stack]]) | ||
* [[RTI]] | * [[RTI]] | ||
It affects the behavior of (possibly incomplete list): | |||
* [[LDX]] | |||
* [[LDY]] | |||
* [[STX]] | |||
* [[STY]] | |||
* [[CPX]] | |||
* [[CPY]] | |||
* [[PHX]] | |||
* [[PHY]] | |||
* [[PLX]] | |||
* [[PLY]] | |||
* [[INX]] | |||
* [[INY]] | |||
* [[DEX]] | |||
* [[DEY]] | |||
* [[TXY]] | |||
* [[TYX]] | |||
* [[TXS]] | |||
* [[TSX]] | |||
In [[emulation mode]], the x flag becomes the [[break flag]]. | |||
There are no BXS or BXC instructions that examine this flag. | |||
=== See Also === | === See Also === | ||
* [[Memory/Accumulator Select]] | * [[Memory/Accumulator Select]] | ||
* [[X Index Register]] | |||
* [[Y Index Register]] | |||
=== | === Reference === | ||
* [[Eyes & Lichty]], | * [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422], Table 18.2. 65x Flags. | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Flags]] | [[Category:Flags]] | ||
[[Category:65c816 additions]] | [[Category:65c816 additions]] | ||
Latest revision as of 21:38, 16 August 2024
Index Register Select (X) is a flag in the processor status register (bit 4) of the 65c816. It indicates how wide the index registers are:
- When clear, both index registers are 16 bits wide. It can only be clear in native mode.
- When set or in emulation mode, both index registers are 8 bits wide.
It is not possible to control the width of the two index registers individually.
It can be affected by:
- REP (clears it if bit 4 of operand is set)
- SEP (sets it if bit 4 of operand is set)
- PLP (pops it off the stack)
- RTI
It affects the behavior of (possibly incomplete list):
In emulation mode, the x flag becomes the break flag.
There are no BXS or BXC instructions that examine this flag.
See Also
Reference
- Eyes & Lichty, page 422, Table 18.2. 65x Flags.