Memory/Accumulator Select: Difference between revisions

Latest revision as of 21:40, 16 August 2024

The Memory/Accumulator Select (M) flag is bit 5 of the 65c816's processor status register. It indicates whether the accumulator is 8 or 16 bits wide:

When clear, the accumulator is 16 bits wide. It can only be clear in native mode.
When set, the accumulator is 8 bits wide, but the high byte (B) is still retained. This is the case after reset because the processor is in emulation mode.

It can be affected by:

REP (clears it if bit 5 of operand is set)
SEP (sets it if bit 5 of operand is set)
PLP (pops it off the stack)
RTI

It affects the behavior of (possibly incomplete list):

But it does not affect XBA, TDC, TCD, TCS, or TSC.

There are no BMS or BMC instructions that examine this flag.

Reference

Eyes & Lichty, page 422, Table 18.2. 65x Flags.

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-The '''Memory/Accumulator Select''' flag exists in the [[processor status register]].  It indicates whether the [[accumulator]] is 8 or 16 bits wide.
+The '''Memory/Accumulator Select''' (M) flag is bit 5 of the [[65c816]]'s [[processor status register]].  It indicates whether the [[accumulator]] is 8 or 16 bits wide:
-When clear, the accumulator is 16 bits wide.
+* When clear, the accumulator is 16 bits wide.  It can only be clear in [[native mode]].
-When set, the accumulator is 8 bits wide, but the high byte is still retained.
+* When set, the accumulator is 8 bits wide, but the high byte (B)  is still retained.  This is the case after reset because the processor is in [[emulation mode]].
+It can be affected by:
+* [[REP]] (clears it if bit 5 of operand is set)
+* [[SEP]] (sets it if bit 5 of operand is set)
+* [[PLP]] (pops it off the [[stack]])
+* [[RTI]]
+It affects the behavior of (possibly incomplete list):
+* [[LDA]]
+* [[STA]]
+* [[STZ]]
+* [[ADC]]
+* [[SBC]]
+* [[BIT]]
+* [[CMP]]
+* [[PHA]]
+* [[PLA]]
+* [[LSR]]
+* [[ASL]]
+* [[ROR]]
+* [[ROL]]
+* [[ORA]]
+* [[AND]]
+* [[EOR]]
+* [[INC]]
+* [[DEC]]
+* [[TSB]]
+* [[TRB]]
+But it does not affect [[XBA]], [[TDC]], [[TCD]], [[TCS]], or [[TSC]].
+There are no BMS or BMC instructions that examine this flag.
 === See Also ===
 * [[Index Register Select]]
+=== Reference ===
+* [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422], Table 18.2. 65x Flags.
 [[Category:ASM]]
 [[Category:Flags]]
 [[Category:65c816 additions]]