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CPU Data Bus: Difference between revisions
From SnesLab
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* [[S-CPU]] pins 60 to 67 | * [[S-CPU]] pins 60 to 67 | ||
* [[WRAM]] | * [[WRAM]] pins 2-5 and 60-63 | ||
* [[S-SMP]] pins 38-45 | * [[S-SMP]] pins 38-45 | ||
* [[Cartridge Slot]] pins 19-22 and 50-53 | * [[Cartridge Slot]] pins 19-22 and 50-53 | ||
Latest revision as of 20:03, 18 August 2024
The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It also how memory is accessed with commands like LDA and STA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:
- S-CPU pins 60 to 67
- WRAM pins 2-5 and 60-63
- S-SMP pins 38-45
- Cartridge Slot pins 19-22 and 50-53
- PPU1 pins 14-21
- PPU2 pins 8-15
- Expansion Port pins 11 to 18
which are the exact same set of components that the SNES bus is connected to.
See Also
External Links
- Figure 2-22-1 Super NES Functional Block Diagram on page 2-22-2 of Book I of the official Super Nintendo development manual