Memory/Accumulator Select: Difference between revisions

Latest revision as of 21:40, 16 August 2024

The Memory/Accumulator Select (M) flag is bit 5 of the 65c816's processor status register. It indicates whether the accumulator is 8 or 16 bits wide:

When clear, the accumulator is 16 bits wide. It can only be clear in native mode.
When set, the accumulator is 8 bits wide, but the high byte (B) is still retained. This is the case after reset because the processor is in emulation mode.

It can be affected by:

It affects the behavior of (possibly incomplete list):

But it does not affect XBA, TDC, TCD, TCS, or TSC.

There are no BMS or BMC instructions that examine this flag.

@@ Line 1: / Line 1: @@
-The '''Memory/Accumulator Select''' (M) flag exists in the [[processor status register]] (bit 5) of the [[65c816]].  It indicates whether the [[accumulator]] is 8 or 16 bits wide:
+The '''Memory/Accumulator Select''' (M) flag is bit 5 of the [[65c816]]'s [[processor status register]].  It indicates whether the [[accumulator]] is 8 or 16 bits wide:
 * When clear, the accumulator is 16 bits wide.  It can only be clear in [[native mode]].
@@ Line 6: / Line 6: @@
 It can be affected by:
-* [[REP]] (might clear it)
+* [[REP]] (clears it if bit 5 of operand is set)
-* [[SEP]] (might set it)
+* [[SEP]] (sets it if bit 5 of operand is set)
-* [[PLP]]
+* [[PLP]] (pops it off the [[stack]])
 * [[RTI]]
-It affects the behavior of (incomplete list):
+It affects the behavior of (possibly incomplete list):
 * [[LDA]]
@@ Line 18: / Line 18: @@
 * [[ADC]]
 * [[SBC]]
+* [[BIT]]
+* [[CMP]]
 * [[PHA]]
 * [[PLA]]
@@ Line 24: / Line 26: @@
 * [[ROR]]
 * [[ROL]]
+* [[ORA]]
+* [[AND]]
+* [[EOR]]
+* [[INC]]
+* [[DEC]]
+* [[TSB]]
+* [[TRB]]
-But it does not affect [[XBA]], [[TDC]], or [[TCD]].
+But it does not affect [[XBA]], [[TDC]], [[TCD]], [[TCS]], or [[TSC]].
 There are no BMS or BMC instructions that examine this flag.