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CPU Data Bus: Difference between revisions

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(more correct name for sound chip)
(mention this is connected to same set of components as SNES bus)
Line 8: Line 8:
* [[PPU2]]
* [[PPU2]]
* [[Expansion Port]]
* [[Expansion Port]]
which are the exact same set of components that the [[SNES bus]] is connected to.


=== See Also ===
=== See Also ===
* [[Address Bus A]]
* [[Address Bus A]]
* [[Address Bus B]]


=== External Links ===
=== External Links ===

Revision as of 17:30, 29 December 2023

The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:

which are the exact same set of components that the SNES bus is connected to.

See Also

External Links

  1. page 2-22-2 of the official Super Nintendo development manual