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CPU Data Bus: Difference between revisions
From SnesLab
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# Figure 2-22-1 Super NES Functional Block Diagram on [https://archive.org/details/SNESDevManual/book1/page/n98 page 2-22-2] of the official Super Nintendo development manual | # Figure 2-22-1 Super NES Functional Block Diagram on [https://archive.org/details/SNESDevManual/book1/page/n98 page 2-22-2 of Book I] of the official Super Nintendo development manual | ||
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[[Category:SNES Hardware]] | [[Category:SNES Hardware]] | ||
[[Category:Buses]] | [[Category:Buses]] | ||
Revision as of 03:00, 13 July 2024
The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:
which are the exact same set of components that the SNES bus is connected to.
See Also
External Links
- Figure 2-22-1 Super NES Functional Block Diagram on page 2-22-2 of Book I of the official Super Nintendo development manual