X Index Register: Difference between revisions
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On the [[S-SMP]] it is always 8 bits wide. It is the divisor for division commands.<sup>[2]</sup> | On the [[S-SMP]] it is always 8 bits wide. It is the divisor for division commands.<sup>[2]</sup> | ||
On the [[65c816]], it may be 8 or 16 bits wide | On the [[65c816]], it may be 8 or 16 bits wide: | ||
* When the [[index register select]] flag is clear, X is 16 bit | |||
* When the index register select flag is set, X is 8 bit | |||
Indexing may cross bank boundaries.<sup>[1]</sup> In [[emulation mode]] it is always 8 bits wide. | |||
Unlike the [[Y index register]], the value of the [[stack pointer]] can be transferred to/from X with [[TXS]] and [[TSX]]. | Unlike the [[Y index register]], the value of the [[stack pointer]] can be transferred to/from X with [[TXS]] and [[TSX]]. | ||
Revision as of 15:28, 16 August 2024
The X Index Register on 65x processors often holds the current index when iterating over things. It can be incremented or decremented by one with INX or DEX, but there is no instruction to add or subtract more than one. Although INX and DEX can affect the negative flag, the indexed addressing modes always interpret the bit pattern in the X index register as a non-negative integer.
On the S-SMP it is always 8 bits wide. It is the divisor for division commands.[2]
On the 65c816, it may be 8 or 16 bits wide:
- When the index register select flag is clear, X is 16 bit
- When the index register select flag is set, X is 8 bit
Indexing may cross bank boundaries.[1] In emulation mode it is always 8 bits wide.
Unlike the Y index register, the value of the stack pointer can be transferred to/from X with TXS and TSX.
It is not specified to have any particular value after reset.
See Also
References
- https://wilsonminesco.com/816myths
- 8.1.2 of page 3-8-4 of Book I of the official Super Nintendo development manual