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CPU Data Bus: Difference between revisions

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The '''CPU Data Bus''', (drawn in brown in the colorized [[jwdonal schematic]]), is the 8-bit data bus that moves data around during a [[DMA]].  It also how memory is accessed with commands like [[LDA]] and [[STA]].  It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." <sup>[1]</sup>  It is connected to:
The '''CPU Data Bus''', (drawn in brown in the colorized [[jwdonal schematic]]), is the 8-bit data bus that moves data around during a [[DMA]].  It also how memory is accessed with commands like [[LDA]] and [[STA]].  It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." <sup>[1]</sup>  It is connected to:


* [[S-CPU]]
* [[S-CPU]] pins 60 to 67
* [[WRAM]]
* [[WRAM]]
* [[S-SMP]]
* [[S-SMP]]

Revision as of 19:54, 18 August 2024

The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It also how memory is accessed with commands like LDA and STA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:

which are the exact same set of components that the SNES bus is connected to.

See Also

External Links

  1. Figure 2-22-1 Super NES Functional Block Diagram on page 2-22-2 of Book I of the official Super Nintendo development manual