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Direct Page Addressing: Difference between revisions
From SnesLab
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* [[Direct Page Bit Addressing]] | * [[Direct Page Bit Addressing]] | ||
=== | === References === | ||
* [[Eyes & Lichty]], page 389: https://archive.org/details/0893037893ProgrammingThe65816/page/n415 | * [[Eyes & Lichty]], page 389: https://archive.org/details/0893037893ProgrammingThe65816/page/n415 | ||
* lbid, page 114: https://archive.org/details/0893037893ProgrammingThe65816/page/n140 | * lbid, page 114: https://archive.org/details/0893037893ProgrammingThe65816/page/n140 | ||
* section 3.5.17 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf | |||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Addressing Modes]] | [[Category:Addressing Modes]] | ||
[[Category:65c816 additions]] | [[Category:65c816 additions]] | ||
Revision as of 16:38, 27 June 2024
Direct Page Addressing is an addressing mode that is supported by the 65c816 and SPC700.
The operand specifies which byte of the direct page to access.
Supported by 24 instructions:
- ADC (opcode 65)
- SBC (opcode E5)
- EOR (opcode 45)
- ASL (opcode 06)
- LSR (opcode 46)
- INC (opcode E6)
- DEC (opcode C6)
- BIT (opcode 24)
- CMP (opcode C5)
- CPX (opcode E4)
- CPY (opcode C4)
- ORA (opcode 05)
- AND (opcode 25)
- LDA (opcode A5)
- LDX (opcode A6)
- LDY (opcode A4)
- ROL (opcode 26)
- ROR (opcode 66)
- STA (opcode 85)
- STX (opcode 86)
- STY (opcode 84)
- STZ (opcode 64)
- TRB (opcode 14)
- TSB (opcode 04)
See Also
References
- Eyes & Lichty, page 389: https://archive.org/details/0893037893ProgrammingThe65816/page/n415
- lbid, page 114: https://archive.org/details/0893037893ProgrammingThe65816/page/n140
- section 3.5.17 of 65c816 datasheet, https://westerndesigncenter.com/wdc/documentation/w65c816s.pdf