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Index Register Select: Difference between revisions

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(TXS, TSX)
(8 bits wide in emulation mode)
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* When clear, both index registers are 16 bits wide.  It can only be clear in [[native mode]].
* When clear, both index registers are 16 bits wide.  It can only be clear in [[native mode]].
* When set, both index registers are 8 bits wide.
* When set or in [[emulation mode]], both index registers are 8 bits wide.


It is not possible to control the width of the two index registers individually.
It is not possible to control the width of the two index registers individually.

Revision as of 15:31, 16 August 2024

Index Register Select (X) is a flag in the processor status register (bit 4) of the 65c816. It indicates how wide the index registers are:

  • When clear, both index registers are 16 bits wide. It can only be clear in native mode.
  • When set or in emulation mode, both index registers are 8 bits wide.

It is not possible to control the width of the two index registers individually.

It can be affected by:

It affects the behavior of (incomplete list):

In emulation mode, the x flag becomes the break flag.

There are no BXS or BXC instructions that examine this flag.

See Also

Reference