We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
CPU Data Bus: Difference between revisions
From SnesLab
(→External Links: bullet point to numbering) |
(linkify jwdonal schematic) |
||
| Line 1: | Line 1: | ||
The '''CPU Data Bus''', (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a [[DMA]]. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to: | The '''CPU Data Bus''', (drawn in brown in the colorized [[jwdonal schematic]]), is the 8-bit data bus that moves data around during a [[DMA]]. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to: | ||
* [[S-CPU]] | * [[S-CPU]] | ||
Revision as of 07:21, 13 July 2023
The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:
External Links
- page 2-22-2 of the official Super Nintendo development manual