CPU Data Bus

The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It also how memory is accessed with commands like LDA and STA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." ^[1] It is connected to:

• S-CPU pins 60 to 67
• WRAM
• S-SMP pins 38-45
• Cartridge Slot pins 19-22 and 50-53
• PPU1 pins 14-21
• PPU2 pins 8-15
• Expansion Port pins 11 to 18

which are the exact same set of components that the SNES bus is connected to.

See Also

• Address Bus A

External Links

1. Figure 2-22-1 Super NES Functional Block Diagram on page 2-22-2 of Book I of the official Super Nintendo development manual