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CPU Data Bus: Difference between revisions
From SnesLab
(see also address buses) |
(mention this is connected to same set of components as SNES bus) |
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* [[S-CPU]] | * [[S-CPU]] | ||
* [[WRAM]] | * [[WRAM]] | ||
* [[ | * [[S-SMP]] | ||
* [[Cartridge Slot]] | * [[Cartridge Slot]] | ||
* [[PPU1]] | * [[PPU1]] | ||
* [[PPU2]] | * [[PPU2]] | ||
* [[Expansion Port]] | * [[Expansion Port]] | ||
which are the exact same set of components that the [[SNES bus]] is connected to. | |||
=== See Also === | === See Also === | ||
* [[Address Bus A]] | * [[Address Bus A]] | ||
=== External Links === | === External Links === | ||
Latest revision as of 17:30, 29 December 2023
The CPU Data Bus, (drawn in brown in the colorized jwdonal schematic), is the 8-bit data bus that moves data around during a DMA. It is denoted CD0~7 in Figure 2-22-1 "Super NES Functional Block Diagram." [1] It is connected to:
which are the exact same set of components that the SNES bus is connected to.
See Also
External Links
- page 2-22-2 of the official Super Nintendo development manual