Processor Status Register: Difference between revisions

Latest revision as of 14:31, 16 August 2024

The Processor Status Register (P) is on the 65c816 and contains several flags:

It can be pulled from the stack via PLP and RTI.

There are nine instructions that directly modify these flags, including:^[3]

REP (can clear multiple)
SEP (can set multiple)
CLC
SEC
CLD
SED
CLI
SEI
CLV

LDP does not exist, and STP does not store the register anywhere.

Several other instructions affect the flags as a side effect. The only transfer instructions that do not modify these flags are TCS and TXS.

These instructions do not modify any status flags:

BCC
BCS
BEQ
BMI
BNE
BPL
BRA
BRL
BVC
BVS
JMP
JSL
JSR
MVN
MVP
NOP
PEA
PEI
PER
PHA
PHB
PHD
PHK
PHP (fullsnes claims the break flag is set)
PHX
PHY
RTL
RTS
STA
STP
STX
STY
STZ
TCS
TXS
WAI
WDM

References

Table 18.2 Eyes & Lichty, page 422
Figure 17.3, Lbid, page 377
lbid, Status Register Control Instructions, page 262
lbid, page 29

@@ Line 1: / Line 1: @@
-The '''Processor Status Register''' (P) is on the [[65c816]] and contains several flags.
+The '''Processor Status Register''' (P) is on the [[65c816]] and contains several flags:
-=== Reference ===
+* 7: [[Negative Flag]] - N
-* [[Eyes & Lichty]], page 422: https://archive.org/details/0893037893ProgrammingThe65816/page/n448
+* 6: [[Overflow Flag]] - V
+* 5: [[Memory/Accumulator Select]] - M
+* 4: [[Index Register Select]] - X
+* 3: [[Decimal Mode]] - D
+* 2: [[Interrupt Disable Flag]] - I
+* 1: [[Zero Flag]] - Z
+* 0: [[Carry Flag]] - C
+It can be pulled from the [[stack]] via [[PLP]] and [[RTI]].
+There are nine instructions that directly modify these flags, including:<sup>[3]</sup>
+* [[REP]] (can clear multiple)
+* [[SEP]] (can set multiple)
+* [[CLC]]
+* [[SEC]]
+* [[CLD]]
+* [[SED]]
+* [[CLI]]
+* [[SEI]]
+* [[CLV]]
+LDP does not exist, and STP does not store the register anywhere.
+Several other instructions affect the flags as a side effect.  The only transfer instructions that do not modify these flags are [[TCS]] and [[TXS]].
+These instructions do not modify any status flags:
+* [[BCC]]
+* [[BCS]]
+* [[BEQ]]
+* [[BMI]]
+* [[BNE]]
+* [[BPL]]
+* [[BRA]]
+* [[BRL]]
+* [[BVC]]
+* [[BVS]]
+* [[JMP]]
+* [[JSL]]
+* [[JSR]]
+* [[MVN]]
+* [[MVP]]
+* [[NOP]]
+* [[PEA]]
+* [[PEI]]
+* [[PER]]
+* [[PHA]]
+* [[PHB]]
+* [[PHD]]
+* [[PHK]]
+* [[PHP]] ([[fullsnes]] claims the break flag is set)
+* [[PHX]]
+* [[PHY]]
+* [[RTL]]
+* [[RTS]]
+* [[STA]]
+* [[STP]]
+* [[STX]]
+* [[STY]]
+* [[STZ]]
+* [[TCS]]
+* [[TXS]]
+* [[WAI]]
+* [[WDM]]
+=== See Also ===
+* [[Emulation Mode Flag]]
+* [[Program Status Word]]
+* [[DSP1 Status Register]]
+* [[PHP]]
+=== References ===
+# Table 18.2 [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422]
+# Figure 17.3, Lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
+# lbid, Status Register Control Instructions, [https://archive.org/details/0893037893ProgrammingThe65816/page/262 page 262]
+# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/29 page 29]
 [[Category:Registers]]
 [[Category:Flags]]
+[[Category:ASM]]