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Eyes & Lichty: Difference between revisions

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(→‎Simple Addressing Modes: linkify admodes)
(→‎Eratta: superscripted 0)
 
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* [[Immediate]]
* [[Immediate]]
* [[Absolute]]
* [[Absolute]]
* Direct Page
* [[Direct Page Addressing|Direct Page]]
* [[Accumulator Addressing|Accumulator]]
* [[Accumulator Addressing|Accumulator]]
* [[Implied]]
* [[Implied]]
Line 16: Line 16:
* [[Block Move Addressing|Block Move]]
* [[Block Move Addressing|Block Move]]


see page 108
see [https://archive.org/details/0893037893ProgrammingThe65816/page/108 page 108]


==== Complex Addressing Modes ====
==== Complex Addressing Modes ====


* Absolute Indexed with X
* [[Absolute Indexed by X]]
* Absolute Indexed with Y
* [[Absolute Indexed by Y]]
* Direct Page Indexed with X
* [[Direct Page Indexed by X]]
* Direct Page Indexed with Y
* [[Direct Page Indexed by Y]]
* Direct Page Indirect Indexed with Y
* [[Direct Page Indirect Indexed by Y]]
* Direct Page Indexed Indirect with X
* [[Direct Page Indexed Indirect by X]]
* Absolute Indexed Indirect
* [[Absolute Indexed Indirect]]
* Direct Page
* Non-zero Direct Page
* Absolute Long Indexed With X
* [[Absolute Long Indexed by X]]
* Direct Page Indirect Long Indexed with Y
* [[Direct Page Indirect Long Indexed by Y]]
* Stack Relative
* [[Stack Relative]]
* Stack Relative Indirect Indexed with Y
* [[Stack Relative Indirect Indexed by Y]]


see page 197
see [https://archive.org/details/0893037893ProgrammingThe65816/page/197 page 197]


=== Eratta ===
=== Eratta ===
* page 497 recommends making sure the carry flag is already set, or to set it with [[SEC]] prior to doing a [[SBC]] to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
Applicable to the 2015 edition:
* On page 498, opcode F5 has a "0" superscript on the # of cycles column.
* The [[stack]] diagram for [[RTI]] has the old [[status register]] value on the opposite side of the stack as the diagram for [[COP]]
* [https://archive.org/details/0893037893ProgrammingThe65816/page/75 page 75] says the 65c816 has 25 different addressesing modes, but the datasheet says there are 24
* [https://archive.org/details/0893037893ProgrammingThe65816/page/94 Page 94] says the 65c816 has three push instructions that do not alter registers: [[PEA]], [[PEI]], and [[PER]].  But there are more than three, for example [[PHA]].
* [[PLB]] is not the only instruction that modifies the [[data bank register]]; [[MVP]] and [[MVN]] do too - see section 7.18 of the 65c816 datasheet
* In the section on [[accumulator addressing]], a sentence implies that all read-modify-write instructions are unary, but [[TRB]] and [[TSB]] are not.
* [https://archive.org/details/0893037893ProgrammingThe65816/page/497 page 497] recommends making sure the carry flag is already set, or to set it with [[SEC]] prior to doing a [[SBC]] to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
* [https://archive.org/details/0893037893ProgrammingThe65816/page/510 Page 510] on [[TCD]] and page 512 on [[TDC]] mentions the [[direct page register]], but this is missing from the index
* In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no.  Many readers would find a check mark less confusing.
* In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no.  Many readers would find a check mark less confusing.
* The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having [[Direct Page Addressing]] anyway "for consistency."
* The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having [[Direct Page Addressing]] anyway "for consistency."
* The 65c02 datasheet does mention [[WAI]] and [[STP]] are supported (page 532 has them listed as unavailable)
* The [[addressing mode]] for [[WDM]] is missing, but the datasheet says it is [[Implied]]
* Assemblers are described as requiring the [[signature byte]] for [[COP]], but on the next page it says the signature byte is optional
* The page on [[PLA]] has a typo that says the 65x pull instructions "set" the zero and negative flags; it should say "affect."


=== Quick Links ===
=== Quick Links ===
Line 64: Line 76:
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n251 The Basic Building Block: The Subroutine]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n251 The Basic Building Block: The Subroutine]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n275 Interrupts and System Control Instructions]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n275 Interrupts and System Control Instructions]
=====[https://archive.org/details/0893037893ProgrammingThe65816/page/n291 Part IV Applications]=====
====[https://archive.org/details/0893037893ProgrammingThe65816/page/n291 Part IV Applications]====
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n293 Selected Code Samples]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n293 Selected Code Samples]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n325 DEBUG16 - A 65816 Programming Tool]
*[https://archive.org/details/0893037893ProgrammingThe65816/page/n325 DEBUG16 - A 65816 Programming Tool]

Latest revision as of 17:15, 22 October 2024

"Eyes & Lichty" is scene slang for the excellent manual "Programming the 65816 Including the 6502, 65C02, and 65802" by David Eyes & Ron Lichty. It may be the best unofficial textbook on SNES programming, due in no small part to the fact that the Ricoh 5A22 is based on the 65c816 and the SPC700 is based on the 6502.

Addressing Mode

Eyes & Lichty divides the 65c816's various addressing modes into two groups: simple and complex. Simple addressing modes are explained first and require the processor to do little effective address calculation. They are:

Simple Addressing Modes

see page 108

Complex Addressing Modes

see page 197

Eratta

Applicable to the 2015 edition:

  • On page 498, opcode F5 has a "0" superscript on the # of cycles column.
  • The stack diagram for RTI has the old status register value on the opposite side of the stack as the diagram for COP
  • page 75 says the 65c816 has 25 different addressesing modes, but the datasheet says there are 24
  • Page 94 says the 65c816 has three push instructions that do not alter registers: PEA, PEI, and PER. But there are more than three, for example PHA.
  • PLB is not the only instruction that modifies the data bank register; MVP and MVN do too - see section 7.18 of the 65c816 datasheet
  • In the section on accumulator addressing, a sentence implies that all read-modify-write instructions are unary, but TRB and TSB are not.
  • page 497 recommends making sure the carry flag is already set, or to set it with SEC prior to doing a SBC to "avoid subtracting the carry flag" but it should say "to avoid subtracting one"
  • Page 510 on TCD and page 512 on TDC mentions the direct page register, but this is missing from the index
  • In the tables that show which MPU supports which instructions, an "X" denotes yes and a " " denotes no. Many readers would find a check mark less confusing.
  • The Rockwell 65c02 does not have a direct page, but the four Rockwell instructions are listed as having Direct Page Addressing anyway "for consistency."
  • The 65c02 datasheet does mention WAI and STP are supported (page 532 has them listed as unavailable)
  • The addressing mode for WDM is missing, but the datasheet says it is Implied
  • Assemblers are described as requiring the signature byte for COP, but on the next page it says the signature byte is optional
  • The page on PLA has a typo that says the 65x pull instructions "set" the zero and negative flags; it should say "affect."

Quick Links

Part I Basics

Part II Architecture

Part III Tutorial

Part IV Applications

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