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Processor Status Register: Difference between revisions

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The '''Processor Status Register''' (P) is on the [[65c816]] and contains several flags:
The '''Processor Status Register''' (P) is on the [[65c816]] and contains several flags:


* [[Negative Flag]] - N
* 7: [[Negative Flag]] - N
* [[Overflow Flag]] - V
* 6: [[Overflow Flag]] - V
* [[Memory/Accumulator Select]] - M
* 5: [[Memory/Accumulator Select]] - M
* [[Index Register Select]] - X
* 4: [[Index Register Select]] - X
* [[Decimal Mode]] - D
* 3: [[Decimal Mode]] - D
* [[Interrupt Disable Flag]] - I
* 2: [[Interrupt Disable Flag]] - I
* [[Zero Flag]] - Z
* 1: [[Zero Flag]] - Z
* [[Carry Flag]] - C
* 0: [[Carry Flag]] - C


It can be pulled from the [[stack]] via [[PLP]] and [[RTI]].
It can be pulled from the [[stack]] via [[PLP]] and [[RTI]].


There are nine instructions that directly modify these flags, including:<sup>[3]</sup>
There are nine instructions that directly modify these flags, including:<sup>[3]</sup>
* [[REP]]
* [[REP]] (can clear multiple)
* [[SEP]]
* [[SEP]] (can set multiple)
* [[CLC]]
* [[CLC]]
* [[SEC]]
* [[SEC]]
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* [[CLV]]
* [[CLV]]


The only transfer instructions that do not modify these flags are [[TCS]] and [[TXS]].
LDP does not exist, and STP does not store the register anywhere.
 
Several other instructions affect the flags as a side effect.  The only transfer instructions that do not modify these flags are [[TCS]] and [[TXS]].
 
These instructions do not modify any status flags:
* [[BCC]]
* [[BCS]]
* [[BEQ]]
* [[BMI]]
* [[BNE]]
* [[BPL]]
* [[BRA]]
* [[BRL]]
* [[BVC]]
* [[BVS]]
* [[JMP]]
* [[JSL]]
* [[JSR]]
* [[MVN]]
* [[MVP]]
* [[NOP]]
* [[PEA]]
* [[PEI]]
* [[PER]]
* [[PHA]]
* [[PHB]]
* [[PHD]]
* [[PHK]]
* [[PHP]] ([[fullsnes]] claims the break flag is set)
* [[PHX]]
* [[PHY]]
* [[RTL]]
* [[RTS]]
* [[STA]]
* [[STP]]
* [[STX]]
* [[STY]]
* [[STZ]]
* [[TCS]]
* [[TXS]]
* [[WAI]]
* [[WDM]]


=== See Also ===
=== See Also ===
* [[Emulation Mode Flag]]
* [[Program Status Word]]
* [[Program Status Word]]
* [[DSP1 Status Register]]
* [[DSP1 Status Register]]
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=== References ===
=== References ===
# Table 18.2 [[Eyes & Lichty]], page 422: https://archive.org/details/0893037893ProgrammingThe65816/page/422
# Table 18.2 [[Eyes & Lichty]], [https://archive.org/details/0893037893ProgrammingThe65816/page/422 page 422]
# Figure 17.3, Lbid, page 377: https://archive.org/details/0893037893ProgrammingThe65816/page/377
# Figure 17.3, Lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# page 262, https://archive.org/details/0893037893ProgrammingThe65816/page/n288
# lbid, Status Register Control Instructions, [https://archive.org/details/0893037893ProgrammingThe65816/page/262 page 262]
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/29 page 29]


[[Category:Registers]]
[[Category:Registers]]
[[Category:Flags]]
[[Category:Flags]]
[[Category:ASM]]

Latest revision as of 14:31, 16 August 2024

The Processor Status Register (P) is on the 65c816 and contains several flags:

It can be pulled from the stack via PLP and RTI.

There are nine instructions that directly modify these flags, including:[3]

LDP does not exist, and STP does not store the register anywhere.

Several other instructions affect the flags as a side effect. The only transfer instructions that do not modify these flags are TCS and TXS.

These instructions do not modify any status flags:

See Also

References

  1. Table 18.2 Eyes & Lichty, page 422
  2. Figure 17.3, Lbid, page 377
  3. lbid, Status Register Control Instructions, page 262
  4. lbid, page 29
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