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Processor Status Register: Difference between revisions
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There are nine instructions that directly modify these flags, including:<sup>[3]</sup> | There are nine instructions that directly modify these flags, including:<sup>[3]</sup> | ||
* [[REP]] | * [[REP]] (can clear multiple) | ||
* [[SEP]] | * [[SEP]] (can set multiple) | ||
* [[CLC]] | * [[CLC]] | ||
* [[SEC]] | * [[SEC]] | ||
Revision as of 02:01, 10 August 2024
The Processor Status Register (P) is on the 65c816 and contains several flags:
- 7: Negative Flag - N
- 6: Overflow Flag - V
- 5: Memory/Accumulator Select - M
- 4: Index Register Select - X
- 3: Decimal Mode - D
- 2: Interrupt Disable Flag - I
- 1: Zero Flag - Z
- 0: Carry Flag - C
It can be pulled from the stack via PLP and RTI.
There are nine instructions that directly modify these flags, including:[3]
LDP does not exist, and STP does not store the register anywhere.
Several other instructions affect the flags as a side effect. The only transfer instructions that do not modify these flags are TCS and TXS.
These instructions do not modify any status flags:
- BCC
- BCS
- BEQ
- BMI
- BNE
- BPL
- BRA
- BRL
- BVC
- BVS
- JMP
- JSL
- JSR
- MVN
- MVP
- NOP
- PEA
- PEI
- PER
- PHA
- PHB
- PHD
- PHK
- PHP (fullsnes claims the break flag is set)
- PHX
- PHY
- RTL
- RTS
- STA
- STP
- STX
- STY
- STZ
- TCS
- TXS
- WAI
- WDM
See Also
References
- Table 18.2 Eyes & Lichty, page 422
- Figure 17.3, Lbid, page 377
- lbid, Status Register Control Instructions, page 262