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Processor Status Register: Difference between revisions

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# Figure 17.3, Lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# Figure 17.3, Lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/377 page 377]
# lbid, Status Register Control Instructions, [https://archive.org/details/0893037893ProgrammingThe65816/page/262 page 262]
# lbid, Status Register Control Instructions, [https://archive.org/details/0893037893ProgrammingThe65816/page/262 page 262]
# lbid, [https://archive.org/details/0893037893ProgrammingThe65816/page/29 page 29]


[[Category:Registers]]
[[Category:Registers]]
[[Category:Flags]]
[[Category:Flags]]
[[Category:ASM]]
[[Category:ASM]]

Latest revision as of 14:31, 16 August 2024

The Processor Status Register (P) is on the 65c816 and contains several flags:

It can be pulled from the stack via PLP and RTI.

There are nine instructions that directly modify these flags, including:[3]

LDP does not exist, and STP does not store the register anywhere.

Several other instructions affect the flags as a side effect. The only transfer instructions that do not modify these flags are TCS and TXS.

These instructions do not modify any status flags:

See Also

References

  1. Table 18.2 Eyes & Lichty, page 422
  2. Figure 17.3, Lbid, page 377
  3. lbid, Status Register Control Instructions, page 262
  4. lbid, page 29