Processor Status Register

The Processor Status Register (P) is on the 65c816 and contains several flags:

• 7: Negative Flag - N
• 6: Overflow Flag - V
• 5: Memory/Accumulator Select - M
• 4: Index Register Select - X
• 3: Decimal Mode - D
• 2: Interrupt Disable Flag - I
• 1: Zero Flag - Z
• 0: Carry Flag - C

It can be pulled from the stack via PLP and RTI.

There are nine instructions that directly modify these flags, including:^[3]

• REP
• SEP
• CLC
• SEC
• CLD
• SED
• CLI
• SEI
• CLV

LDP does not exist, and STP does not store the register anywhere.

Several other instructions affect the flags as a side effect. The only transfer instructions that do not modify these flags are TCS and TXS.

These instructions do not modify any status flags:

• BCC
• BCS
• BEQ
• BMI
• BNE
• BPL
• BRA
• BRL
• BVC
• BVS
• JMP
• JSL
• JSR
• MVN
• MVP
• NOP
• PEA
• PEI
• PER
• PHA
• PHB
• PHD
• PHK
• PHP (fullsnes claims the break flag is set)
• PHX
• PHY
• RTL
• RTS
• STA
• STP
• STX
• STY
• STZ
• TCS
• TXS
• WAI
• WDM

See Also

• Emulation Mode Flag
• Program Status Word
• DSP1 Status Register
• PHP

References

1. Table 18.2 Eyes & Lichty, page 422: https://archive.org/details/0893037893ProgrammingThe65816/page/422
2. Figure 17.3, Lbid, page 377: https://archive.org/details/0893037893ProgrammingThe65816/page/377
3. lbid, Status Register Control Instructions, page 262, https://archive.org/details/0893037893ProgrammingThe65816/page/262