We've just updated MediaWiki and its underlying software. If anything doesn't look or work quite right, please mention it to us. --RanAS
Negative Flag: Difference between revisions
From SnesLab
(added PLP) |
(→See Also: zero flag) |
||
| Line 52: | Line 52: | ||
=== See Also === | === See Also === | ||
* [[Zero Flag]] | |||
* [[Overflow Flag]] | * [[Overflow Flag]] | ||
* [[Carry Flag]] | * [[Carry Flag]] | ||
Revision as of 22:21, 12 August 2024
The Negative Flag (N) is bit 7 of the 65c816's status register. It is set or cleared to reflect the most significant bit of arithmetic results or transferred values. Although there are no dedicated SEN or CLN instructions to set or clear it, it can be set with SEP and cleared with REP:
SEP #$80 REP #$80
These instructions also affect the negative flag (this bulleted list being 38 long):
- ADC
- AND
- ASL
- BIT
- CMP
- CPX
- CPY
- DEC
- DEX
- DEY
- EOR
- INC
- INX
- INY
- LDA
- LDX
- LDY
- ORA
- PLA
- PLB
- PLD
- PLP (missing from the Labiak textbook's list)
- PLX
- PLY
- ROL
- ROR
- SBC
- TAX
- TAY
- TCD
- TDC
- TSC
- TSX
- TXA
- TXY
- TYA
- TYX
- XBA
Also, LSR always clears the negative flag because it also shifts a zero into the operand's most significant bit, making it non-negative.
BPL and BMI examine the negative flag to decide whether or not to branch.
See Also
Reference
- Labiak, Willam. Page 109