Zero Flag: Difference between revisions

Latest revision as of 03:08, 20 September 2024

The Zero Flag (Z) is bit 1 of the 65c816's status register. It indicates whether the last value computed, transferred, or pulled is zero: set if it is and clear if not. Although there are no dedicated SEZ or CLZ instructions to set or clear it, it can be directly set with SEP and cleared with REP:

SEP #$02
REP #$02

It is also affected by these 41 instructions:

The BEQ and BNE instructions examine the zero flag to decide whether or not to branch. Push instructions do not affect the zero flag.

The SPC700 and Super FX chips also have a zero flag.

The zero flag is invalid in decimal mode on the NMOS 6502, but it is valid in the 65c816's decimal mode.

References

Labiak, page 108
Eyes & Lichty, "Branching Based on the Zero Flag" on page 146
Table 7-1 Caveats of 65c816 datasheet

@@ Line 1: / Line 1: @@
-The '''Zero Flag''' exists on the [[65c816]].
+The '''Zero Flag''' (Z) is bit 1 of the [[65c816]]'s [[status register]].  It indicates whether the last value computed, transferred, or pulled is zero: set if it is and clear if not.  Although there are no dedicated SEZ or CLZ instructions to set or clear it, it can be directly set with [[SEP]] and cleared with [[REP]]:
-=== Reference ===
+<pre>
-* Labiak, page 108 https://archive.org/details/Programming_the_65816/page/n118
+SEP #$02
+REP #$02
+</pre>
+It is also affected by these 41 instructions:
+* [[ADC]]
+* [[AND]]
+* [[ASL]]
+* [[BIT]]
+* [[CMP]]
+* [[CPX]]
+* [[CPY]]
+* [[DEC]]
+* [[DEX]]
+* [[DEY]]
+* [[EOR]]
+* [[INC]]
+* [[INX]]
+* [[INY]]
+* [[LDA]]
+* [[LDX]]
+* [[LDY]]
+* [[LSR]]
+* [[ORA]]
+* [[PLA]]
+* [[PLB]]
+* [[PLD]]
+* [[PLX]]
+* [[PLY]]
+* [[ROL]]
+* [[ROR]]
+* [[SBC]]
+* [[TAX]]
+* [[TAY]]
+* [[TCD]]
+* [[TCS]]
+* [[TDC]]
+* [[TRB]]
+* [[TSB]]
+* [[TSC]]
+* [[TSX]]
+* [[TXA]]
+* [[TXY]]
+* [[TYA]]
+* [[TYX]]
+* [[XBA]]
+The [[BEQ]] and [[BNE]] instructions examine the zero flag to decide whether or not to branch.  Push instructions do not affect the zero flag.
+The [[SPC700]] and [[Super FX]] chips also have a zero flag.
+The zero flag is invalid in [[decimal mode]] on the NMOS 6502, but it is valid in the 65c816's decimal mode.
+=== See Also ===
+* [[Negative Flag]]
+* [[Carry Flag]]
+* [[Overflow Flag]]
+=== References ===
+* [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n118 page 108]
+* [[Eyes & Lichty]], "Branching Based on the Zero Flag" on [https://archive.org/details/0893037893ProgrammingThe65816/page/146 page 146]
+* Table 7-1 Caveats of 65c816 datasheet
 [[Category:ASM]]
 [[Category:Flags]]
 [[Category:Inherited from 6502]]
+[[Category:Condition Codes]]