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Zero Flag: Difference between revisions
From SnesLab
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=== Reference === | === Reference === | ||
* [[Labiak]], | * [[Labiak]], [https://archive.org/details/Programming_the_65816/page/n118 page 108] | ||
[[Category:ASM]] | [[Category:ASM]] | ||
[[Category:Flags]] | [[Category:Flags]] | ||
[[Category:Inherited from 6502]] | [[Category:Inherited from 6502]] | ||
Revision as of 00:50, 6 August 2024
The Zero Flag (Z) exists on the 65c816 as bit 1 of the status register. Although there are no dedicated SEZ or CLZ instructions to set or clear it, it can be directly set with SEP and cleared with REP. It is also affected by these 41 instructions:
- ADC
- AND
- ASL
- BIT
- CMP
- CPX
- CPY
- DEC
- DEX
- DEY
- EOR
- INC
- INX
- INY
- LDA
- LDX
- LDY
- LSR
- ORA
- PLA
- PLB
- PLD
- PLX
- PLY
- ROL
- ROR
- SBC
- TAX
- TAY
- TCD
- TCS
- TDC
- TRB
- TSB
- TSC
- TSX
- TXA
- TXY
- TYA
- TYX
- XBA
The BEQ and BNE instructions examine the zero flag to decide whether or not to branch.
The SPC700 and Super FX chips also have a zero flag.